The present invention relates generally to a structure for high frequency applications have a substrate on which a glass layer is disposed with improved uniformity and thickness and significantly lower cost compared to prior art.
Printed circuit boards (PCBs) are used extensively in the electronics arts to mount and interconnect discrete electronic components (integrated circuit chips, etc.) to implement a specific function. Commonly, the board substrate is made of polymers and ceramics, although other materials such as silicon or other semiconductors can be used. It is often desirable to electrically isolate certain components mounted on the PCB from each other and from the board substrate. Typically, this is accomplished by applying one or more layers of dielectric material to the surface of the board and then mounting the components on or in the dielectric layers. For high frequency electronic applications, thick dielectrics layers over conductive substrates are needed to form transmission lines.
Common techniques for forming dielectric layers on a wafer of silicon include chemical vapor deposition (CVD) and spin-on-glass (SOG) techniques. These processes are essentially limited to producing dielectric layers of only several microns in thickness, due the to inability to effectively prevent cracking in layers of greater thickness and/or their prohibitively slow formation rates. Because of the limitations of thickness of the dielectric layers produced by the above techniques, capacitive coupling problems are not reduced to acceptable levels. That is, capacitive isolation between the substrate and components is not reduced to an acceptable level. The limited thickness of the dielectric layer prevents its use for transmission line applications. Additionally, many of these processes are incapable of forming a dielectric layer having a sufficiently high dielectric constant (e.g., at least 4.1 at 20 degrees C. and 1 MHz) and sufficiently low loss tangent (e.g., at most 0.06 percent at 20 degrees C. and 1 MHz) to permit use of the resulting board in high performance electronics applications (e.g. microwave and/or other radio frequency circuit applications).
Other techniques used conventionally in the fabrication of glass-on-silicon make use of the bonding of a glass wafer to a silicon wafer. This process has certain advantages, for example the ability to maintain an acceptably thick layer of glass for transmission line use, as well as an acceptably thick layer of glass/silicon during processing to prevent cracking and thus improve yield. Unfortunately, these techniques require a circumferential lip to effectively bond the glass to the silicon. This technique renders, thereby, a portion of the wafer not useful. The techniques discussed herein can be found in U.S. patent application Ser. No. 08/845,726 now U.S. Pat. No. 6,114,716 to Boles, et al. and U.S. Pat. Nos. 5,268,310 and 5,343,070 to Goodrich, et al., the disclosures of which are specifically incorporated herein by reference. Additionally, discontinuities due to pockets or voids in the glass result in unacceptable dielectric properties and result in an unacceptable degradation in the electrical properties of the resultant heterolithic microwave integrated circuit. To this end, at the corners of a silicon pedestal there is a tendency for a void to form between the silicon and the glass. While the technique used to fabricate the HMIC structure shown in the referenced application to Boles, et al., serves to reduce the voids to acceptable levels, the silicon structures forming the pedestals are limited to those formed by wet-etching techniques. To this end, the silicon is monocrystalline and is anisotropically etched to reveal crystalline planes. These planes enable the bonding of glass without significant voids, however there are certain limitations. The presence of these air gaps both limits the size of the pedestals and forces a minimum spacing between pedestals. It has been found that with the technique of fusing the glass and the problems with the air gaps or voids requires the pedestals to be spaced no less than 300 microns apart, with the distance between the pedestals being measured from the near edges of the pedestals at the top of the pedestals. To this end, if the pedestals are spaced too closely, these voids or air gaps become nearly continuous or continuous. This has obvious deleterious effects on the electrical properties of the structure, and significantly adversely affects the adhesion of the glass to the substrate. Thus, the pedestals must be spaced relatively far apart as these factors reduce the number of dies that can be fabricated on a wafer and reduces the number of chips that can be placed on a given substrate. Furthermore, the cost of glass wafers are substantially higher than the cost of the silicon wafer and becomes prohibitively more expensive for wafer diameters larger than 100 mm. Finally, vertical pedestals with substantially right angle corners can not be used due to the large air gaps and poor adhesion of the glass thereto. Another technique for fabricating relatively thick layers of electronics grade glass on silicon substrates at lower cost is as disclosed in U.S. Pat. No. 5,639,325 to Stevens, et al. The patent to Stevens, et al., discusses the use of a slurry of glass powder which is prepared with a variety of carriers to include volatile organic solvents and/or water. Additionally, the use of hydrogen is discussed at an ambient temperature of 800xc2x0 C. This reference to Stevens, et al., while having clear advantages when compared to other techniques for forming a glass layer on a silicon substrate and the article thereby produced compared to the prior techniques, there are certain drawbacks which are inherent in the Stevens, et al. technique. To this end, the reference to Stevens, et al., discloses the use of a particle size of the powder which has an average granular size of about 325 mesh. Particle size as well as variations in the size of the particles can be problematic.
In many applications thin glass layers are required, on the order of 5.8 mils. For example, as is disclosed on U.S. patent application Ser. No. 08/845,726, to Boles et al. referenced above, it is necessary to backfill 5-8 mils of glass in thickness between silicon pedestals which are on the order of 3-4 mils in height. When particle size variation ranges in the order of 5-100 microns, it is difficult to effect this desired thickness without multiple firings. To this end, islands on the order of 1 mil can form on the relatively thin glass layer on the order of 0.5 microns which is formed in the first firing. The process must then be repeated to continually increase the thickness and make more uniform the regions between the islands. The reason that the islands are formed is due to surface energy effects which occur when the powder starts to melt and, due to the variation in size, starts to melt into clumps. Accordingly, it is desirable to have a process to fabricate the relatively thick glass layer on the order of 4-12 mils in a variety of applications in a single firing. Another significant drawback to the technique disclosed in the Stevens, et al. patent, is the fact the hydrogen bubbles of a relatively large size remain in the glass as well, creating xe2x80x9cpockxe2x80x9d marks on the surface. The technique disclosed in the reference to Stevens, et al., has clear advantages over prior techniques of forming glass, particularly in a slurry as the hydrogen bubbles are significantly reduced compared to the air bubbles that form when no firing under partial pressure of hydrogen is effected. However, these craters and bubbles have clear disadvantages in uniformity. The hydrogen bubbles can reduce the electronic performance because the glass is not as uniform of a dielectric as is required in electronics grade, particularly high frequency where capacitive coupling is an issue which must be attended to very carefully. Often, the thickness of the glass is reduced to an undesirable level in order to properly grind and polish the surface.
Accordingly, what is needed is a glass layer disposed on a silicon substrate which has more uniformity and greater thickness than in prior structures.
The present invention relates to a structure for high frequency electronic applications. A substrate, preferably silicon, or other suitable material has a layer of glass material disposed thereon. A ground plane layer can be disposed between the silicon and the glass a layer or, in some applications, disposed beneath the silicon layer. Two terms for such a glass-coated article having glass disposed on a silicon substrate are heterolithic microwave integrated circuit (HMIC) and glass microwave integrated circuit (GMIC). The silicon pedestals of the present disclosure can be doped suitably to be conductive, and the dielectric material disposed about these conductive silicon pedestals form a substrate for the integrated circuit. The dielectric material used in fabricating the dielectric layer between signal lines and elements disposed on top of the glass-coated article and the ground plane for the integrated circuit on the lower surface of either the silicon, or the glass, should have a very precise thickness as well as dielectric properties which are very uniform. The thickness and uniformity are required to properly effect the performance and impedance matching of the integrated circuit to include the transmission lines as well as passive and active components of the integrated circuit. The glass must be a low-loss material at high frequency, and, as stated previously, of a thickness which enables capacitive isolation. To this end, reduction of parasitic capacitance is of critical importance in high frequency integrated circuits, as is well known to one of ordinary skill in the art. In the preferred embodiment of the present disclosure, in which there are silicon pedestals, the silicon pedestals have a height on the order of 3-9 mils. The thickness of the glass layer disposed about the silicon pedestals is on the order of 3-12 mils. The glass material fabricated as described herein has a substantially increased uniformity due to the reduction in bubbles as well as a relatively smooth top surface. By virtue of the reduction in the number and size of the bubbles of gas in the glass, the dielectric properties of the glass are more uniform. Additionally, the fact that the surface of the glass is much more smooth reduces the potential of prior structures to have an unacceptably thin glass layer due to the need to grind the surface smooth. As described herein, often times in prior glass materials the thickness becomes unacceptably reduced. The bubble size achievable with the steps described in Stevens et. al""s patent is approximately the size of the glass powder used, or around 40 mils for 325 mesh glass powder. The density of the bubbles will be very high and most of the bubbles are clustered with others. In the present invention, the bubbles are individual and discrete. To this end, the bubbles which result in the bulk of the glass product of the present invention are significantly reduced in volume when compared to the prior art. Measurements have shown that the bubbles are of an oblong shape with a width on the order of 10-30 microns and a height which is virtually insignificant when compared to the width. This has a direct benefit as the dielectric constant has a uniformity which is identical (within measurement accuracy) to the glass wafers of the prior art. Because the cost of the glass of the present disclosure is drastically reduced when compared to the wafer glass of the prior art, the invention of the present disclosure has a significant advantage over the prior art. In addition the loss tangent has a value which is identical (again within measurement accuracy) to the glass wafer of the prior art. The glass has clear advantages when compared to the bulk wafer glass, and dielectric and loss tangent properties which are the same as the bulk glass, making the glass of the present disclosure a very attractive alternative. In summary therefore, the glass of the present invention has electrical (dielectric and loss tangent) properties which compare very favorably with the wafer glass, and the versatility and reduction in cost when compared to the glass described in the Stevens, et al patent.
The silicon substrate of the present disclosure can take on a number of shapes. To this end, the preferred embodiment of the present disclosure envisions anisotropically etched silicon pedestals. This is effected through a wet-etch technique in which the side surfaces of the pedestals have a specific angle relative to the bottom surface (a commonly used silicon crystalline structure results in an angle of approximately 54 degrees) of the substrate of silicon. This follows directly from the crystalline nature of the monocrystalline material. Alternatively, the silicon substrate could be planar. Finally, pedestals and other structures are envisioned by the present disclosure which have side surfaces which are orthogonal to the bottom surface of the silicon. This is generally done by a dry-etching technique, preferably reactive ion etching, well known to one of ordinary skill in the art. The glass of the present disclosure is readily adhered to such a structure without significant air gaps as plague the prior art. Whether the pedestals have vertical or sloped sidewalls, the air gaps that form in the interface or transition between the horizontal surface of the substrate and the sidewall by the glass adhesion techniques of the wafer-glass to the substrate of the prior art are overcome by the invention of the present disclosure which enables improved electrical properties and good adhesion of the glass to the substrate. This has the advantages of decreased spacing between the pedestals, and thus an increase in the number of dies per wafer and an increase in the number of chips on a substrate. Accordingly, the glass material of the present disclosure enables a variety of applications, as can be readily appreciated by one of ordinary skill in the art.
It is an object of the present invention to have a substantially uniform dielectric glass material with a thickness great enough to reduce parasitic capacitances in high frequency applications.
It is a feature of the present invention to have a glass material which has significantly reduced bubble sizes and number of bubbles in the glass, as a result of the specific glass powder particle size distribution discussed herein.
It is advantage of the present invention to have a glass material for microwave integrated circuits which is disposed on silicon substrates of a wide variety of shapes.